Debugging, Logic Design, Sta, Circuit Design, Physical Verification, PNR, Physical Design, EDA Tools, Optimization, Rtl Design

PnR-Floorplan Macro placement, EM IR understanding and fixes, STA analysis, Util area reduction experiments, ECO cycle, Density Congestion Timing issues and fixes on lower tech nodes 5nm, Physical aware Synthesis using FC, PV closure

redhawk , Perl, Python, Tcl, EMIR sign-off flows, Voltus, electromigration analysis, Totem, chip-package co-simulation, EMIR sign-off methodology, chip-package co-design, PDN planning, PDN architecture planning

static timing analysis, industry-standard EDA tools for physical design and verification, Synthesis, RTL-to-GDS workflows, multi-power domain analysis, low-power design techniques, Place And Route, Clock Tree Synthesis

hardware engineering , Perl Scripting, Sta, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design, PDN Methodology, PPA Targets, Timing Signoff

clock distribution , Clp, PERL, Tcl, low power design, Sta, PERC, Signal Integrity Analysis, LVS, LEC flow, Tape Out, IP integration, Dfm, Timing Closure, Physical Verification, Synthesis, Gds, Tk, cpf, Clock Tree Synthesis, upf, PNR, Physical Design, ERC, DRC, Floorplan

Hard Macros (SerDes), Flip-Chip, PNR, Cadence Tools, Physical Implementation, FDSOI 22nm

PYTHON, routing, PERL, Tcl, power analysis, LVS, physical design methodology, Physical Verification, Logic Synthesis, Noise analysis, DRC, electro migration, Placement, Clock Tree Synthesis