Memory Layout Engineer
Memory Layout Engineer
dignifyd- Posted 4 hours ago
- Be among the first 10 applicants
Job Description
We are looking for an experienced Memory Layout Engineer with a minimum of 3+ years of hands-on experience in Memory Layout Design and Physical Layout implementation. The candidate should have exposure to advanced semiconductor technology nodes, particularly TSMC and/or Samsung process technologies.
Key Responsibilities
- Develop and implement memory layout designs based on design specifications.
- Work on memory layout implementation, optimization, and physical verification.
- Ensure layout quality, design accuracy, and compliance with foundry requirements.
- Collaborate with circuit design, physical design, and verification teams.
- Perform layout-related checks and resolve Design Rule Check (DRC) violations.
- Support layout optimization for advanced technology nodes.
Required Skills & Technical Expertise
- Minimum 3+ years of experience in Memory Layout Design.
- Hands-on experience with advanced semiconductor technology nodes.
- Experience with TSMC and/or Samsung process technologies.
- Understanding of memory layout implementation and physical verification.
- Knowledge of DRC, LVS, and other physical verification concepts is preferred.
Technology Node Requirements
TSMC:
- A14n
- 2nm
- 3nm
- 5nm
Samsung:
- 2nm
- 4nm
More Info
Key Skills
Physical Layout Implementation
Samsung Process Technologies
DRC
Advanced Semiconductor Technology Nodes
Memory Layout Design
About Company
Skills:
shielding , Pvs, Crosstalk, LVS, MUX Control Blocks, Latch-up, Sense Amplifiers, Assura, Memory Compiler, Esd, Critical Signal Routing, Antenna, DRAM, Memory Periphery Circuits, Cadence VLE, Calibre DRC, EM, IR-drop, Sram, Custom Memory Layouts, LVS DRC debugging, Bitcell Arrays, Memory Layout Design, Rom, Flash Memory Layout Design, Wordline Decoders, Rf, ERC
Skills:
Calibre, design-rule constraints, FinFET technology nodes, layout optimization, physical verification methodologies, custom layout design, DRC, Parasitic Extraction, LVS, SRAM memory layout, Cadence Virtuoso
Skills:
Python, Tcl, QRC, StarRC, Skill, ICC, Cadence Virtuoso, Calibre DRC LVS
Skills:
Design for Manufacturability (DFM), Design for Yield (DFY), Shell, PERL, Tcl, Physical verification layout methodologies, Skill, DRC, LVS, Memory Layout, Semiconductor design flows