shielding , Pvs, Crosstalk, LVS, MUX Control Blocks, Latch-up, Sense Amplifiers, Assura, Memory Compiler, Esd, Critical Signal Routing, Antenna, DRAM, Memory Periphery Circuits, Cadence VLE, Calibre DRC, EM, IR-drop, Sram, Custom Memory Layouts, LVS DRC debugging, Bitcell Arrays, Memory Layout Design, Rom, Flash Memory Layout Design, Wordline Decoders, Rf, ERC

Calibre, design-rule constraints, FinFET technology nodes, layout optimization, physical verification methodologies, custom layout design, DRC, Parasitic Extraction, LVS, SRAM memory layout, Cadence Virtuoso

Python, Tcl, QRC, StarRC, Skill, ICC, Cadence Virtuoso, Calibre DRC LVS

Design for Manufacturability (DFM), Design for Yield (DFY), Shell, PERL, Tcl, Physical verification layout methodologies, Skill, DRC, LVS, Memory Layout, Semiconductor design flows