Memory Layout Engineer
Memory Layout Engineer
smartsoc solutions pvt ltd- Posted 17 hours ago
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Job Description
We're Hiring | Memory Layout Engineers
We're looking for experienced Memory Layout Engineers to join our team and work on cutting-edge semiconductor technologies.
Experience: 4+ Years
Location: Bangalore
Key Responsibilities:
- Design memory layouts for various building blocks, including:
- Bit Cell Arrays ,Row Decoders, Column Decoders, Sense Amplifiers, Input/Output (I/O) Blocks
- Integrate top-level memory layouts.
- Perform physical verification using DRC and LVS.
- Ensure layouts comply with Design for Manufacturability (DFM) and Design for Yield (DFY) requirements.
- Analyze layouts for power integrity and signal integrity.
- Develop and maintain automation scripts using PERL, Shell, TCL, or SKILL.
Required Skills:
Strong hands-on experience in Memory Layout for advanced technology nodes.
Expertise in TSMC and/or other process technologies with lower nodes (2nm/3nm/5nm).
Solid understanding of physical verification, layout methodologies, and semiconductor design flows.
Scripting knowledge is an added advantage.
More Info
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Key Skills
About Company
Skills:
Shell, PERL, Tcl, Skill, DRC, LVS, Memory Layout
Skills:
Python, Tcl, QRC, StarRC, Skill, ICC, Cadence Virtuoso, Calibre DRC LVS
Skills:
Shell, PERL, Tcl, Assura, Skill, Memory layout design, Cadence Virtuoso
Skills:
cadence schematic capture , Verification tools - CALIBRE, Cadence Tools, Memory layout design, AI automation in layout, ElectroMigration, Hercules, SKILL Programming, Physical verification LVS, ERC, DRC, Script Programming, Antenna, Chip Integration, Floor-planning, Hierarchy layout