4–6 years of experience in Memory or Custom Layout Design with strong expertise in memory architectures and layout optimization techniques.
Responsibilities:
- Design and optimize memory layouts for high-performance and low-power applications.
- Ensure compliance with FinFET technology requirements and DRC rules.
- Perform physical verification flows (DRC, LVS, ERC) and debug issues effectively.
- Conduct EM/IR analysis and implement necessary fixes.
- Collaborate with circuit design teams to ensure layout accuracy and performance.
- Automate layout processes using scripting languages for improved efficiency.
Technical Skills:
- Strong understanding of memory architectures and layout optimization techniques.
- Hands-on experience with FinFET technology and DRC rules.
- Proficient in physical verification flows (DRC, LVS, ERC) and debugging.
- Experience with EM/IR analysis and fixes.
- Skilled in Cadence Virtuoso and Calibre tools.
- Familiarity with scripting languages for automation and flow customization.
Preferred Skills:
- Knowledge of advanced memory design methodologies.
- Exposure to high-density memory layouts and low-power design techniques.
- Strong problem-solving and analytical skills.
