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Key Responsibilities
Job ID: 148699791
Skills:
Svn, Tcl, Bash, Python, Perl, Version Control, Git, Simulation Tools, Uvm, systemverilog, PCS FEC, high-speed interfaces, dynamic verification, SERDES
Skills:
Object-Oriented Programming (OOP), Verilog, Embedded C, systemverilog, Uvm, VHDL, Specman e, Verification Methodology, IP Verification, SoC Verification
Skills:
teststand , Doors, Uart, Tcp Ip, Spi, Embedded Software, Svn, JIRA, Jama, Can, Arinc, Gitlab, I2c, LabVIEW, Veristand, DO-178 C Level D software, DO-330 Tool Qualification, Teamcenter, Python scripts, PyATE framework
Skills:
Perl, Python, SV – UVM Assertions based verification, RTL debug skills, ARM based system architecture, industry-standard simulation tools, power aware simulation, RTL design verification, Uvm, systemverilog, Firmware emulation, camera verification, Coverage closure, dpi
Skills:
Shell, Perl, Python, simulation and waveform analysis tools, verification methodologies, CPU microarchitecture, Uvm, coverage-driven verification, systemverilog, assertions, debugging skills, formal verification concepts, SVA
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