Svn, Tcl, Bash, Python, Perl, Version Control, Git, Simulation Tools, Uvm, systemverilog, PCS FEC, high-speed interfaces, dynamic verification, SERDES

Object-Oriented Programming (OOP), Verilog, Embedded C, systemverilog, Uvm, VHDL, Specman e, Verification Methodology, IP Verification, SoC Verification

teststand , Doors, Uart, Tcp Ip, Spi, Embedded Software, Svn, JIRA, Jama, Can, Arinc, Gitlab, I2c, LabVIEW, Veristand, DO-178 C Level D software, DO-330 Tool Qualification, Teamcenter, Python scripts, PyATE framework

Perl, Python, SV – UVM Assertions based verification, RTL debug skills, ARM based system architecture, industry-standard simulation tools, power aware simulation, RTL design verification, Uvm, systemverilog, Firmware emulation, camera verification, Coverage closure, dpi

Shell, Perl, Python, simulation and waveform analysis tools, verification methodologies, CPU microarchitecture, Uvm, coverage-driven verification, systemverilog, assertions, debugging skills, formal verification concepts, SVA

C, Makefile, Windows, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools

C, Makefile, Windows, Shell, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, TLM

Gdb, Docker, Git, Linux, Embedded Systems, Python-based test automation, SDV OTA FOTA

Shell, C, Verilog, Python, Uvm, systemverilog