Lead Synthesis Engineer
Lead Synthesis Engineer
leadsoc technologies pvt ltdThis job is no longer accepting applications
Job Description
Lead Synthesis Engineer
Experience Level :- 6yrs to 10yrs
Notice Period :- Immediate to 45 Days
Work Location :- Bangalore
Job Description – Lead Synthesis Engineer (VLSI)
- Worked on 7nm/5nm/Future sub-micron Technologies.
- Hands on experience in Physical Synthesis with Multi corner & Multi-mode, Low Power, Performance and Area Goal using Fusion Compiler or Genus.
- Hands on experience in Logic equivalence check and low power check debugging and clean up using Conformal LEC or Formality.
- Familiar with pre-STA timing analysis using Primetime or Tempus.
- Familiar with low power check using Conformal Low Power or VCLP tool.
- Experience in verifying constraints quality and completeness.
- Understanding of UPF & Low power concepts.
- Familiar with functional ECO flow and implementation.
- Familiar with DFT Insertion and debugging basic DFT issues.
- Co-work with RTL, DFT and PD engineers to meet PPA targets.
- Well versed with TCL/Perl/Shell script.
- Self-starter and highly motivated.
- Strong debugging, initiative and analysis/problem solving skills.
More Info
Key Skills
DFT Insertion
Fusion Compiler
Conformal Low Power
Formality
Tempus
VCLP tool
Logic equivalence check
UPF Low power concepts
pre-STA timing analysis
Genus
functional ECO flow
About Company
Skills:
RTL synthesis, setup hold analysis, advanced SoC design flows, Timing Closure, SDC constraints development, PPA optimization, Cadence Genus
Skills:
synopsys primetime , Static Timing Analysis, Perl, Python, Tcl, SDC constraints, RTL Synthesis, STA timing constraints, ASIC SoC implementation and signoff methodologies, Synopsys Design Compiler, ECOs and timing fixes, critical path analysis, implementation flows, RTL-to-gate synthesis, Fusion Compiler, setup hold analysis, Timing Closure, timing optimization