Role: Lead RTL Design Engineer
Experience: 7 to 13 Years
Location: Bengaluru
Job Description:
- Should be good in Integration of SOC & RTL coding.
- Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC.
- Should be aware of scripting language.
- Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP.
- Should have good understanding of SoC flows.
Primary Skills:
- VHDL, Verilog, Micro-architecture, RTL coding, CDC, Lint, Synthesis, STA, IP development, SoC integration, VCLP, scripting - Perl, Python, Shell, and Tcl.
Secondary Skills:
- Synopsis/Cadence tool flow, ARM Coretex, DMA, DDR, SPI, I2C, UART, AHB/AXI/APB, Ethernet, USB, PCIe, Mipi CSI/DSI, LPDDR.
