Senior Lead RTL Design

RTL Design Engineer with 8+ years of Hands on experiences.

Experience/proficiency in RTL design(Verilog/VHDL) architecture implementation using (coding in) hardware description (RTL) , IP Design, SoC Design and Integration

Should have hands on experience in all the Design aspects, should work independently.

Experience/proficiency in front-end (logic) design of large complex high-speed digital stems from Specification to RTL code signoff

Experience on RTL signoff tools, Lint, CDC, FE BE, Equivalence checks, Spyglass and other equivalent tools

Strong team player & effective in communication

Should ready to work out of Bangalore customer office in all 5 a week.