Search by job, company or skills

Quest Global

Lead -Physical Design Engineer

Save
new job description bg glownew job description bg glow
  • Posted a day ago
  • Be among the first 10 applicants
Early Applicant

Job Description

Job Requirements

At Quest Global, it's not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Key Responsibilities

  • Perform RTL-to-GDSII implementation for complex SoCs and subsytem level Design.
  • Execute floorplanning, placement, CTS, routing, Physical verification , low power checks, IR/EM, Antenna and timing closure.
  • Drive power, performance, and area (PPA) optimization.
  • Conduct physical verification (DRC/LVS) and sign-off checks.
  • Collaborate with RTL, DFT, and verification teams to resolve design issues.
  • Work on multi-voltage, low-power design techniques and UPF/CPF flows.
  • Support ECO implementation and tape-out activities.

Required Skills & Qualifications

  • 10+ years of experience in ASIC/SoC physical design.
  • Strong knowledge of EDA tools ( Cadence, Innovus, Tempus, PrimeTime, Voltus,Calibre, Redhawk, PrimeClouser etc.).
  • Expertise in timing analysis, signal integrity, and power analysis.
  • Experience with advanced nodes (e.g., 16nm, 5nm,4nm, 3nm, 2nm).
  • Familiarity with DFT insertion, low-power design, and multi-clock domain handling.
  • Good understanding of physical verification and manufacturing sign-off.
  • Strong problem-solving and debugging skills.
  • Experience in working on Automotive or Industrial MPU/MCU SoCs (preferred for safety-critical designs and compliance with standards like ISO 26262).
  • Knowledge of EM/IR analysis and reliability checks
  • Familiarity with scripting languages (Tcl, Perl, Python) for flow automation.

Education

Bachelor's or Master's degree in Electrical Engineering, Electronics, or related field.

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.

More Info

Job Type:
Industry:
Employment Type:

About Company

Job ID: 147649873

Similar Jobs

Bengaluru, India

Skills:

ScriptingStatic Timing AnalysisRoutingDesign CompilerprimetimeICC2Synopsys Fusion CompilerLVSCadence GenusInnovusPhysical VerificationExtractionFormal EquivalenceStarRCPlacementFloor-plan Physical ImplementationRTL to GDS2 flowPower-plan SynthesisApache RedhawkMentor Graphics CalibreCrosstalk AnalysisEMIrPhysical DesignTiming ClosureDRCPNR tools

Bengaluru, India

Skills:

clock distribution TclClpPERLGdsSynthesisIP integrationPower and Signal Integrity AnalysisPhysical DesignClock Tree SynthesisERCDRCPNRTape OutExtractionupfDfmTiming Closurelow power designLVSPhysical VerificationcpfFloorplanStaPERCTkLEC flow

Bengaluru, India

Skills:

redhawk ApacheTclPerlRoutingPythonEMCPU physical designPlace And RoutePlacementIrCalibrePPA tradeoffsSynthesisDRCExtractionCadence PrimeTimefloor plan synthesisLVSPhysical VerificationCTSsignoffSynopsys Fusion Compilerfloor-planningphysical design methodologiesTiming ClosureStarRC

Bengaluru, India

Skills:

Cadence InnovusSynthesisEMIRfloorplanningIR drop analysis

Bengaluru, India

Skills:

DcElectrical checksPnR toolsSTA toolsPhysical VerificationICCChip tape outsPhysical DesignInnovusSign-off optimizationsGenusSign-off convergence