Perl, Python, Tcl, OCV, primetime, Fusion Compiler, ICC2, SI Crosstalk, ECO flows, MMMC, Timing Closure, POCV, AOCV, Clock Tree Synthesis

redhawk , Python Scripting, Shell, Perl, Verilog, Tcl, full-chip aspects, Fusion compiler, Formal equivalence, PTPX, ICC2, signoff, IP integration, Timing Verification, Physical Design, primetime, timing convergence, VHDL, PNR, Low Power Checks, EDA Tools

clock distribution , Clp, PERL, Tcl, low power design, Sta, PERC, Signal Integrity Analysis, LVS, LEC flow, Tape Out, IP integration, Dfm, Timing Closure, Physical Verification, Synthesis, Gds, Tk, cpf, Clock Tree Synthesis, upf, PNR, Physical Design, ERC, DRC, Floorplan

Perl Scripting, Tcl, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, IC design, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, High Frequency Design, Power Gating, PDN Methodology, PPA Targets, Timing Signoff