Lead Physical Design Engineer

Lead Physical Design Engineer

Experience: 6–12 Years

Location: Bengaluru

About the Role

We're looking for an experienced Physical Design Engineer with deep expertise in Static Timing Analysis (STA) to drive timing closure and full-chip implementation for cutting-edge SoCs across advanced technology nodes. You will work closely with RTL, Synthesis, CTS, and Signoff teams to deliver high-performance, power-efficient silicon.

What You'll Do

• Drive full-chip and block-level Physical Design from floorplanning through signoff.
• Own Static Timing Analysis (STA), timing closure, ECO implementation, and signoff across multiple PVT corners and modes.
• Perform timing analysis for setup/hold, clock skew, OCV, SI, Crosstalk, and multi-mode multi-corner (MMMC) scenarios.
• Optimize placement, CTS, routing, and timing to achieve aggressive PPA targets.
• Collaborate with RTL, Synthesis, DFT, and Signoff teams to resolve timing bottlenecks.
• Analyze and fix timing violations using ECO methodologies while maintaining design integrity.
• Drive convergence for timing, power, congestion, and physical signoff.

What We're Looking For

• 6–12 years of hands-on experience in Physical Design and STA.
• Strong expertise in PrimeTime, ICC2/Fusion Compiler, and industry-standard implementation flows.
• Solid understanding of Timing Closure, MMMC, OCV/AOCV/POCV, SI, Crosstalk, Clock Tree Synthesis, and ECO flows.
• Experience with advanced technology nodes (3nm/5nm/7nm/12nm/16nm) is highly preferred.
• Strong scripting skills in Tcl, Perl, or Python.
• Experience in full-chip integration and signoff is a plus.
• Excellent debugging, analytical, and cross-functional collaboration skills.

Preferred Qualifications

• Experience with high-performance CPU, GPU, AI/ML, Networking, or SoC designs.
• Exposure to low-power implementation (UPF/CPF) and physical signoff (DRC/LVS/EMIR) is an advantage.
• Proven ability to mentor engineers and drive technical execution across complex projects.