Lead Engineer
Lead Engineer
Tessolve- Posted a month ago
- Be among the first 10 applicants
Job Description
- About Us:
- Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs.
- Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. Tessolve's design services include solutions on advanced process nodes with a healthy eco-system relationship with EDA, IP, and foundries. Our front-end design strengths integrated with the knowledge from the backend flow, allows Tessolve to catch design flaws ahead in the cycle, thus reducing expensive re-design costs, and risks. We actively invest in the R&D center of excellence initiatives such as 5G, mmWave, Silicon photonics, HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-end product design services in the embedded domain from concept to manufacturing under an ODM model with application expertise in Avionics, Automotive, Industrial and Medical segments. Tessolve's Embedded Engineering services enable customers a faster time-to-market through deep domain expertise, innovative ideas, diverse embedded hardware & software services, and built-in infrastructure with world-class lab facilities.
- Tessolve's clientele includes Tier 1 clients across multiple market segments, 9 of the top 10 semiconductor companies, start-ups, and government entities. We have a global presence over 12 countries with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose.
- For more details, visit https://www.tessolve.com/
- Job Overview
- Join our team as a leader in physical design, spearheading the development of advanced SoC/ASIC projects. Your leadership will drive essential design processes, enhance collaboration across various engineering teams, and ensure top-notch design quality. Make a significant impact by mentoring engineers and implementing best practices that push the boundaries of innovation. This role is critical in delivering cutting-edge technology within the semiconductor industry.
- Job Designation Physical Design Team Lead
- Job Location Bangalore
- Experience : 7 to 10
- What you'll do
- Lead the physical design for SoC/ASIC projects.
- Drive floorplanning, placement, and timing closure.
- Collaborate with engineering teams for design quality.
- Perform power analysis and integrity checks.
- Manage sign-off activities for design verification.
- Who you are
- Skilled in SoC/ASIC design processes.
- Proficient in power analysis and IR drop checks.
- Collaborative and effective communicator.
- Dedicated mentor for team development.
- Committed to innovation and best practices.
- Tessolve Semiconductor Private Limited, as well as its affiliates and subsidiaries (Tessolve) does not require job applicants to make any payments at any stage of the hiring process. Any request for payment in exchange for a job opportunity at Tessolve is fraudulent and should be ignored. If you receive any such communication, we strongly advise you to refrain from making any payments and to promptly report the incident to us at [Confidential Information]. Tessolve is not responsible for any losses incurred due to such fraudulent activities
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Key Skills
IR drop checks
SoC ASIC design processes
About Company
Skills:
Acceptance Testing, Ems, Data Migration, Coding Skills, Dms, SCADA, ots, Real-time utility environments, Planning applications, Load flow contingency analysis, Real-time operational context, Data population, Power-system network applications
Skills:
Shell, Tcl Scripting, Python, Routing, Perl, Sta, CTS, Signoff, OCV, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, Signal Integrity, LVS, IR Drop, Physical Verification, MCMM, POCV, Setup Hold, RTL-to-GDSII Physical Design flow, floorplanning, Post-route Optimization, Placement Optimization, EM, Power Planning, Eco, Timing Closure, DRC, AOCV, Synopsys ICC2
Skills:
verification flows, DFT architecture, ATPG, scan chains, ASIC SOC design, Scan Insertion, transition fault models, ATPG pattern generation, DFT Scan verification, Fault Simulation
Skills:
redhawk , Tcl Scripting, Python, timing reports, primetime, Fusion Compiler, floorplanning, CTS routing, LEC, Tempus, Cadence Innovus, Physical Verification, setup hold debugging, Voltus, tile block PnR, Asic Physical Design, Calibre, Optimisation, StarRC, Placement, Parasitic Extraction, Synopsys ICC2
Skills:
Static timing analysis, Linux, Lsf, Bitbucket, Git, Unix, Splunk, AI ML, Python, Jenkins, EDA Tools, convolutional Networks, make, GenAI, SW development, CI CD process, Implementation, design layout constraints, DesignSync, debug tools, Power-aware flows, UPF, Clocks, Design Verification, cdc, reinforcement learning, Graph Neural Networks, SDC, Dft, RDC