Acceptance Testing, Ems, Data Migration, Coding Skills, Dms, SCADA, ots, Real-time utility environments, Planning applications, Load flow contingency analysis, Real-time operational context, Data population, Power-system network applications

Shell, Tcl Scripting, Python, Routing, Perl, Sta, CTS, Signoff, OCV, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, Signal Integrity, LVS, IR Drop, Physical Verification, MCMM, POCV, Setup Hold, RTL-to-GDSII Physical Design flow, floorplanning, Post-route Optimization, Placement Optimization, EM, Power Planning, Eco, Timing Closure, DRC, AOCV, Synopsys ICC2

verification flows, DFT architecture, ATPG, scan chains, ASIC SOC design, Scan Insertion, transition fault models, ATPG pattern generation, DFT Scan verification, Fault Simulation

redhawk , Tcl Scripting, Python, timing reports, primetime, Fusion Compiler, floorplanning, CTS routing, LEC, Tempus, Cadence Innovus, Physical Verification, setup hold debugging, Voltus, tile block PnR, Asic Physical Design, Calibre, Optimisation, StarRC, Placement, Parasitic Extraction, Synopsys ICC2

Static timing analysis, Linux, Lsf, Bitbucket, Git, Unix, Splunk, AI ML, Python, Jenkins, EDA Tools, convolutional Networks, make, GenAI, SW development, CI CD process, Implementation, design layout constraints, DesignSync, debug tools, Power-aware flows, UPF, Clocks, Design Verification, cdc, reinforcement learning, Graph Neural Networks, SDC, Dft, RDC

Visual Studio, Power Electronics, FPGA PCB design, Simulation and analysis of electrical systems, Power hardware development and testing, Hardware design and build experience in power electronics systems, Grid integration, Power converter and control for high frequency high voltage and high power applications, HVDC, Signal Processing, Electrical system Power electronic converters