What you'll do:
- Develop, test, maintain, and improve design IPs for optimal Power, Performance, and Area (PPA).
- Implement functionality in SystemC/C++ and ensure designs meet stringent Latency, Throughput, Area, and Power goals.
- Perform comprehensive power, area, and performance trade-off analyses to identify the most efficient solutions.
- Leverage High-Level Synthesis (HLS) to rapidly iterate and evaluate a wide range of possible implementations, narrowing down to the best-suited version.
- Drive coverage closure and meet all other sign-off criteria for IPs within a high-level design and verification environment.
- Author detailed design documents that clearly articulate your architectural and implementation choices.
What you'll bring:
- 5-10 years of experience in RTL design (Verilog, SystemVerilog, digital microarchitecture).
- A Bachelor's/Master's degree pr PhD Scholars with 6 years of relevant experience are preferred.
- Proven experience in breaking down complex digital signal processing algorithms into Micro/RTL architecture, while effectively managing cost and quality trade-offs.
- Proficiency in coding with C/C++/Python/Bash.
- Experience with High-Level Synthesis (HLS) for ASICs or FPGAs is a significant advantage.
- Knowledge of basic processor architecture.
- Experience with the full ASIC design cycle (from specification through bring-up) is preferred.
We are Siemens
A collection of over 377,000 minds building the future, one day at a time, in over 200 countries. We're dedicated to equality and welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow!
