C
Lead Design Engineer
C
Lead Design Engineer
Cadence Design Systems (India) Pvt LtdThis job is no longer accepting applications
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Proficient in RTL coding, datapath designs, complex FIFO design Strong knowledge on complete design flows and rigorous checks before delivery to other teams or customers ex- LINT, SDC, CDC, DFT, CLP, Synth and trial PnR Good experience of micro architecture, design, synthesize for a complex SerDes IP in various technology nodes. Desired Protocols knowledge - USB, PCie, MIPI(DPHY), HDMI/Display Work closely with Analog design teams to co-develop algorithms, feedback design loops as well as high speed critical digital circuits Good understanding of working with signal processing IPs in terms of knowing calibrations, plls, dividers.
We're doing work that matters. Help us solve what others can't.
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Key Skills
About Company
Skills:
conformal lec , Unix, Clp, Perl, Linux, Python, Tcl, LEC, CPF-based power intent, UPF, Cadence Genus, ASIC synthesis, IEEE 1801, low-power verification flows
Skills:
clocking , Arm, Trace32, Multimedia, Microprocessors, Computer Architecture, interconnect safety, Synthesis, Security, ARM Debug, Ace, RTL design flow, Verilog RTL coding, RISC-V, APB, Axi, Reset, ATB, BUS Protocols, Chip Assembly, LINT, RTL signoff tools, Serial Interfaces, cdc, ARM CoreSight ETM, IP Integration, Arm Cortex-M A R processor-based SoC debug infrastructure, External Bus Interfaces, RDC, System modes
Skills:
conformal lec , Unix, Clp, Linux, Tcl, Python, Perl, Cadence Genus, UPF, LEC, IEEE 1801, CPF-based power intent, low-power verification flows, ASIC synthesis
Skills:
Perl, Tcl Scripting, Python, System Verilog, Synopsys Mentor VIPs, PCIe Gen3, random constraint-based testing, verification methodologies, performance power optimization, SMMU, CXL 1.1, Coresight architecture, assertion-based verification, Uvm, UPF, CHI protocols, Axi, formal verification, power-aware verification, coverage-driven testing, SVA
Skills:
routing, RTL-to-GDS flows, Rtl Design, floorplanning, Physical Verification methodologies, Cadence, LVS, Physical Design, EDA Tools, ERC, Timing Closure, DRC, Placement, Synopsys, Siemens tools, Clock Tree Synthesis