Lead Design Engineer
Lead Design Engineer
CADENCE- Posted a month ago
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Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Core Responsibilities
Testbench Architecture: Design scalable, reusable, and robust verification environments. This includes developing Bus Functional Models (BFMs), monitors, scoreboards, and checkers.
Feature Extraction: Analyze architectural specifications to identify critical features and corner cases that require rigorous testing.
Debug: Lead the root-cause analysis of complex design bugs, collaborating closely with design engineers to implement fixes.
Constraint Random Testing: Implement constrained-random stimulus generation to explore the design space beyond directed tests.
Formal Verification: Utilize formal tools to prove specific properties or find deep-seated bugs that simulation might miss.
Gate-Level Simulation (GLS): Oversee simulations on the synthesized netlist to verify timing and reset behavior.
Sign-off: Define the definition of done and provide final technical approval for the verification phase.
Soft Skills and Leadership
Mentorship: Guiding junior engineers on coding standards and debugging techniques.
Cross-functional Collaboration: Acting as the primary technical point of contact between the design, architecture, and emulation teams.
Project Management: Managing timelines, identifying risks in the verification schedule, and prioritizing tasks to meet project deadlines.
Required Qualifications
B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field
4–6 years of hands-on DV experience in semiconductor/ASIC/SoC companies
We're doing work that matters. Help us solve what others can't.
Core Responsibilities
- Strategy and Architecture
Testbench Architecture: Design scalable, reusable, and robust verification environments. This includes developing Bus Functional Models (BFMs), monitors, scoreboards, and checkers.
Feature Extraction: Analyze architectural specifications to identify critical features and corner cases that require rigorous testing.
- Execution and Technical Leadership
Debug: Lead the root-cause analysis of complex design bugs, collaborating closely with design engineers to implement fixes.
Constraint Random Testing: Implement constrained-random stimulus generation to explore the design space beyond directed tests.
Formal Verification: Utilize formal tools to prove specific properties or find deep-seated bugs that simulation might miss.
- Metric Management
Gate-Level Simulation (GLS): Oversee simulations on the synthesized netlist to verify timing and reset behavior.
Sign-off: Define the definition of done and provide final technical approval for the verification phase.
Soft Skills and Leadership
Mentorship: Guiding junior engineers on coding standards and debugging techniques.
Cross-functional Collaboration: Acting as the primary technical point of contact between the design, architecture, and emulation teams.
Project Management: Managing timelines, identifying risks in the verification schedule, and prioritizing tasks to meet project deadlines.
Required Qualifications
B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field
4–6 years of hands-on DV experience in semiconductor/ASIC/SoC companies
We're doing work that matters. Help us solve what others can't.
More Info
Key Skills
checkers
constraint random testing
monitors
scoreboards
About Company
Skills:
DDR, System Verilog, IP Verification, HBM, Design Verification, Environment Development, Functional Verification, Memory IP, Uvm, GDDR, Test Plan Generation
Skills:
power optimization , static timing analysis, Verilog, Uvm, place-and-route, Synthesis, SV-based testbenches, verification methodologies, power optimization techniques, Simulation, Timing Analysis, Cadence, coverage-driven verification, systemverilog, Rtl Design, VHDL, EDA Tools, Mentor Graphics, digital design flow, Synopsys
Skills:
Debugging, Ovm, Verilog, System Verilog, Problem-solving skills, Functional Verification Coverage, Uvm, formal verification, DDR-PHY Design Verification, Design Verification of complex IPs, Low Power Verification, Gate Simulation
Skills:
Soc Architecture, Physical design interaction, SoC integration, Formal verification techniques and tools, Verilog RTL development, UPF and low-power methodologies
Skills:
Pcie, Verilog, Ethernet, LINT, cdc, UALink, CHI, High-speed interconnects, RTL, systemverilog, CCIX, Synthesis, CXL, Timing, Microarchitecture