Lead Design Engineer
Lead Design Engineer
CADENCE- Posted a month ago
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Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
- 4+ years of Design Verification experience with SV/UVM
- Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
- Design Verification experience verifying complex designs and leading projects from concept to verification closure.
- Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
- Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.
More Info
Key Skills
IP Verification
HBM
Environment Development
Memory IP
GDDR
Test Plan Generation
About Company
Skills:
Phase Interpolator, CAD tools for circuit simulation, Cadence tool experience, CMOS design, Bias and Bandgap Voltage Regulators, SERDES, jitter and signal equalization techniques, High Speed Clock Distribution, Low jitter PLL, layout and physical verification
Skills:
Vcs, Perl, Verilog, System Verilog, Python, Tcl, LINT, cdc, Xcelium, spyglass, RDC, Questa, Questa CDC
Skills:
power optimization , static timing analysis, Verilog, Uvm, place-and-route, Synthesis, SV-based testbenches, verification methodologies, power optimization techniques, Simulation, Timing Analysis, Cadence, coverage-driven verification, systemverilog, Rtl Design, VHDL, EDA Tools, Mentor Graphics, digital design flow, Synopsys
Skills:
Debugging, Ovm, Verilog, System Verilog, Problem-solving skills, Functional Verification Coverage, Uvm, formal verification, DDR-PHY Design Verification, Design Verification of complex IPs, Low Power Verification, Gate Simulation
Skills:
Soc Architecture, Physical design interaction, SoC integration, Formal verification techniques and tools, Verilog RTL development, UPF and low-power methodologies