DDR, System Verilog, IP Verification, HBM, Design Verification, Environment Development, Functional Verification, Memory IP, Uvm, GDDR, Test Plan Generation

power optimization , static timing analysis, Verilog, Uvm, place-and-route, Synthesis, SV-based testbenches, verification methodologies, power optimization techniques, Simulation, Timing Analysis, Cadence, coverage-driven verification, systemverilog, Rtl Design, VHDL, EDA Tools, Mentor Graphics, digital design flow, Synopsys

Debugging, Ovm, Verilog, System Verilog, Problem-solving skills, Functional Verification Coverage, Uvm, formal verification, DDR-PHY Design Verification, Design Verification of complex IPs, Low Power Verification, Gate Simulation

Soc Architecture, Physical design interaction, SoC integration, Formal verification techniques and tools, Verilog RTL development, UPF and low-power methodologies

Pcie, Verilog, Ethernet, LINT, cdc, UALink, CHI, High-speed interconnects, RTL, systemverilog, CCIX, Synthesis, CXL, Timing, Microarchitecture

Design Compiler, primetime, Vivado, SDC timing constraints, Genus, Tempus, VLIW, FPGA prototyping, systemverilog