Scripting, Verilog, System Verilog, Pcie, LINT, Synthesis, Uvm, cdc, RTL integration, ASIC development flows, CXL, Genus STA, Verification

power optimization , Verilog, static timing analysis, Uvm, Synopsys, SV-based testbenches, Timing Analysis, Mentor Graphics, digital design flow, EDA Tools, coverage-driven verification, systemverilog, Rtl Design, Cadence, VHDL, Simulation

Vcs, Pcie, Python, Perl, Ethernet, Tcl, Xcelium, Uvm, Testbench Architecture, LPDDR4, Functional Coverage, Verdi, UCIe, systemverilog, Axi, MIPI, Constrained Random Verification, APB, DVE, USB4, USB3, Questa, CXL, DDR5, DDR4, AHB, SVA

Soc Architecture, System Verilog, digital design concepts, UVM Universal Verification Methodology, debugging using waveforms and logs

rtl development , virtualization, Clp, LINT, DFT verification, cdc, IP SoC design, silicon debug, SoC Design Verilog RTL coding, PLDRC, formal verification, coherency protocols, micro-architecture, Digital Design