Search by job, company or skills

C

Lead Design Engineer

Cadence
Bengaluru
4-9 Years
Save
new job description bg glownew job description bg glow
  • Posted 10 hours ago
  • Be among the first 10 applicants
Early Applicant
Quick Apply

Job Description

Key Responsibilities

  • Develop and execute verification plans for IP, subsystem, and SoC-level designs.
  • Create detailed test plans and functional coverage strategies to ensure design completeness.
  • Develop and close functional coverage, code coverage, and assertions for complex ASIC designs.
  • Perform design verification using SystemVerilog/UVM or equivalent HVL methodologies.
  • Work on post-silicon validation and bring-up activities to ensure silicon readiness.
  • Debug complex verification and design issues across IP and system levels.
  • Collaborate with cross-functional teams to ensure verification quality and schedule adherence.
  • Apply scripting and automation techniques to improve verification efficiency.
  • Ensure compliance with verification processes and best practices.
  • Contribute to continuous improvement of verification methodology and flows.

More Info

Job Type:
Permanent Job
Industry:
Software Engineering
Role:
Other Roles
Function:
Others
Employment Type:
Full time

About Company

Cadence

Job ID: 148699001

Jobs by Skill - IT
Jobs by Skill - Non IT
International Jobs
Last Updated: 04-06-2026 07:09:24 AM
Homejobs in Bengaluru / BangaloreLead Design Engineer

Similar Jobs

Lead Design Engineer

Cadence
C
Bengaluru

Skills:

Verilog, Usb, Pcie, RTL Coding, systemverilog, Datapath design, FIFO design, Microarchitecture, SERDES, MIPI D-PHY

Early Applicant

Lead Design Engineer

CADENCE
Bengaluru, India

Skills:

System Verilog, Design Verification, Functional Verification, Environment Development, Uvm, Test Plan Generation

Lead Design Engineer - Digital IP

Larsen & Toubro
Bengaluru, India

Skills:

Vcs, Tcl, Verilog, System Verilog, Python, Perl, Sec, Questa, spyglass, LINT, Xcelium, cdc, Jasper-FPV, Questa CDC, RDC

Lead Design Engineer

ALTEN Calsoft Labs
Bengaluru, India

Skills:

power optimization , Verilog, static timing analysis, Uvm, Synopsys, SV-based testbenches, Timing Analysis, Mentor Graphics, digital design flow, EDA Tools, coverage-driven verification, systemverilog, Rtl Design, Cadence, VHDL, Simulation

Lead Design Engineer

Cadence Design Systems
Bengaluru

Skills:

Verilog, Physical Design, Analog Electronics