Lead Design Engineer

Key Responsibilities

• Develop RTL designs for complex digital and mixed-signal IPs, including datapath logic, controllers, and high-performance FIFOs
• Create and review microarchitecture specifications for SerDes and high-speed interface IPs
• Perform RTL coding, design verification support, synthesis, and implementation activities
• Ensure design quality through comprehensive design checks including LINT, SDC, CDC, DFT, CLP, synthesis, and trial place-and-route (PnR) validation
• Collaborate closely with analog design teams to co-develop calibration algorithms, feedback control loops, and high-speed digital circuitry
• Design and optimize digital logic for performance, power, and area targets across multiple technology nodes
• Support integration and bring-up of SerDes and interface IPs within larger SoC environments
• Analyze and resolve design issues related to timing, functionality, and implementation closure
• Work with signal processing and mixed-signal blocks involving PLLs, dividers, calibration engines, and clocking architectures
• Participate in design reviews and ensure adherence to established design methodologies and quality standards