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Job ID: 148623797
Skills:
SystemVerilog Assertions (SVA), Verilog, Computer Architecture, systemverilog, Uvm, Digital Design, Micro-architecture, Rtl Design, Design Verification
Skills:
Pcie, Verilog, System Verilog, Scripting, LINT, cdc, Genus STA, RTL integration, Uvm, Synthesis, Verification, CXL, ASIC development flows
Skills:
Vcs, Tcl, Verilog, System Verilog, Python, Perl, Sec, Questa, spyglass, LINT, Xcelium, cdc, Jasper-FPV, Questa CDC, RDC
Skills:
power optimization , Verilog, static timing analysis, Uvm, Synopsys, SV-based testbenches, Timing Analysis, Mentor Graphics, digital design flow, EDA Tools, coverage-driven verification, systemverilog, Rtl Design, Cadence, VHDL, Simulation
Skills:
Physical Verification, Physical Design
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