Phase Interpolator, CAD tools for circuit simulation, Cadence tool experience, CMOS design, Bias and Bandgap Voltage Regulators, SERDES, jitter and signal equalization techniques, High Speed Clock Distribution, Low jitter PLL, layout and physical verification

Vcs, Perl, Verilog, System Verilog, Python, Tcl, LINT, cdc, Xcelium, spyglass, RDC, Questa, Questa CDC

power optimization , static timing analysis, Verilog, Uvm, place-and-route, Synthesis, SV-based testbenches, verification methodologies, power optimization techniques, Simulation, Timing Analysis, Cadence, coverage-driven verification, systemverilog, Rtl Design, VHDL, EDA Tools, Mentor Graphics, digital design flow, Synopsys

Debugging, Ovm, Verilog, System Verilog, Problem-solving skills, Functional Verification Coverage, Uvm, formal verification, DDR-PHY Design Verification, Design Verification of complex IPs, Low Power Verification, Gate Simulation

Soc Architecture, Physical design interaction, SoC integration, Formal verification techniques and tools, Verilog RTL development, UPF and low-power methodologies

Shell, Tcl Scripting, Python, Routing, Perl, Sta, CTS, Signoff, OCV, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, Signal Integrity, LVS, IR Drop, Physical Verification, MCMM, POCV, Setup Hold, RTL-to-GDSII Physical Design flow, floorplanning, Post-route Optimization, Placement Optimization, EM, Power Planning, Eco, Timing Closure, DRC, AOCV, Synopsys ICC2