FPGA Design, Verilog, systemverilog, Xilinx Vivado, altera quartus, Peripheral Protocols

Fast Fourier Transform, Verilog, Digital Signal Processing, System Verilog, complex algebra, OFDM, FPGA development, Xilinx FPGA architectures, AXI4 Stream, Rtl Design, Vivado, baseband processing, AXI4 Lite, linear algebra

hardware bring up , Tcl, C, FPGA Design, System Verilog, Python, test benches, Rtl Design, UVM verification flow, Synthesis, Timing Closure, Verification, Debug, Simulation

code coverage , perl, C, Regression Testing, Ovm, Pcie, Ethernet, Python, Uvm, systemverilog, Axi, DDR protocols, RTL simulators, X-propagation, functional coverage

Fpga, Algorithm Development, VLSI CAD software, Statistical Techniques, VLSI architecture, RTL design using Verilog, systemverilog, Xilinx Vivado

Algorithm Development, Fpga, Statistical Techniques, VLSI architecture, Xilinx Vivado, VLSI CAD software, systemverilog, RTL design using Verilog

Fpga, Verilog, Algorithm Development, VLSI CAD software, CAD flows, VLSI architecture, Statistical Techniques, systemverilog, Xilinx Vivado