DFT Engineer
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Role and Responsibilities: Scan Insertion, ATPG Pattern generation, Coverage Analysis, Unit delay, Timing simulations, SoC level DFT Activities
Skill Requirements: Scan Insertion, ATPG Pattern generation, Coverage Analysis, Unit delay, Timing simulations, SoC level DFT Activities
Experience: 4 to 8 years
Notice Period-Immediate to 15Days
Qualifications: B.Tech/B.E/M.Tech/M.E
Job ID: 153627577
Skills:
Jasper, Perl, Verilog, Debugging, Python, Tcl, Xcelium, Memory Test methodologies, Modus, Scan Insertion, VHDL, ATPG, Genus, silicon bring-up
Skills:
Unix, Report Automation, Svn, Git, Shell, Perl, Linux, Verilog, Python, Tcl, MBIST, log parsing, TetraMax, DFT fundamentals, systemverilog, Scan compression, Scan architecture, Synopsys DFT Compiler, flow orchestration, ATPG, Cadence Modus, LBIST, TestMAX
Skills:
synopsys tools , Tessent, Fault coverage analysis, Scan ATPG
Skills:
boundary scan standards, scan chain insertion and optimization techniques, silicon debug and failure analysis processes
Skills:
Soc Architecture, Tcl, Python, Perl, HDLs, MBIST, ATPG flow implementation, UPF, Cadence digital implementation tools, DFT architecture definition, Tempus, CPF, Scan, Genus, tessent DFT, JTAG boundary scan
