Jasper, Perl, Verilog, Debugging, Python, Tcl, Xcelium, Memory Test methodologies, Modus, Scan Insertion, VHDL, ATPG, Genus, silicon bring-up

Unix, Report Automation, Svn, Git, Shell, Perl, Linux, Verilog, Python, Tcl, MBIST, log parsing, TetraMax, DFT fundamentals, systemverilog, Scan compression, Scan architecture, Synopsys DFT Compiler, flow orchestration, ATPG, Cadence Modus, LBIST, TestMAX

synopsys tools , Tessent, Fault coverage analysis, Scan ATPG

boundary scan standards, scan chain insertion and optimization techniques, silicon debug and failure analysis processes

Soc Architecture, Tcl, Python, Perl, HDLs, MBIST, ATPG flow implementation, UPF, Cadence digital implementation tools, DFT architecture definition, Tempus, CPF, Scan, Genus, tessent DFT, JTAG boundary scan

boundary scan , Vcs, System Verilog, Memory BIST, JTAG protocols, ATPG, Logic Equivalency checking, Scan and BIST architectures, Gate level simulation debugging

Vcs, ATE patterns, Scan Insertion, JTAG protocols, Tessent, Gate level simulation, ATPG, Post-silicon validation, P1687, TestMax, TetraMax