DFT Engineer
DFT Engineer
TeslaThis job is no longer accepting applications
Job Description
About the Role:
Tesla's Silicon Development Group is seeking a DFT Engineer
to drive Design-for-Test across the design-to-production lifecycle
for custom ASICs. In this role, you will own testability from design through silicon bring-up and high-volume manufacturing. You will advance state-of-the-art methodologies in test, debug, and safety to achieve high coverage, exceptional quality, and ultra-low DPPM—while optimizing test cost at scale.
Responsibilities:
Define and implement DFT features at RTL and gate levels using in-house flows Partner with physical design teams to achieve timing and design closure with DFT constraints Execute block-level scan insertion, ATPG, coverage analysis, and simulations Perform full-chip pattern retargeting, validation, and sign-off Drive design improvements to enhance test coverage and diagnosability Collaborate with test and product engineering on pattern delivery, silicon bring-up, debug, and characterization
Requirements:
Strong understanding of DFT methodologies including compressed scan, MBIST, loopback, and boundary scan across digital logic, embedded memory, and IO/PHY domains Solid knowledge of JTAG, IEEE 1500, and IEEE 1687; familiarity with BSDL, ICL, and PDL is a plus Proven expertise in ATPG, coverage analysis, and both zero-delay and SDF-based simulations Experience with industry-standard DFT tools such as Cadence Modus/Genus or Siemens Tessent Strong foundation in Verilog, digital logic design, circuit fundamentals, and timing analysis Proficiency in scripting (TCL, Python, or Perl) Experience with MBIST implementation, repair algorithms, and memory test strategies is a plus Exposure to SerDes and mixed-signal DFT techniques (e.g., IOBIST, loopbacks) is a plus Post-silicon experience including pattern conversion, bring-up, debug, and characterization is a plus Bachelor's or Master's degree in Electrical or Computer Engineering (or equivalent experience)
Tesla's Silicon Development Group is seeking a DFT Engineer
to drive Design-for-Test across the design-to-production lifecycle
for custom ASICs. In this role, you will own testability from design through silicon bring-up and high-volume manufacturing. You will advance state-of-the-art methodologies in test, debug, and safety to achieve high coverage, exceptional quality, and ultra-low DPPM—while optimizing test cost at scale.
Responsibilities:
More Info
Key Skills
DFT methodologies
Siemens Tessent
circuit fundamentals
compressed scan
IEEE 1500
IEEE 1687
ATPG coverage analysis
Cadence Modus
Genus
SDF-based simulations
About Company
Skills:
Jtag, Perl, Python, NVIDIA custom tools, Memory BIST, SV, ATPG, Uvm
Skills:
Jtag, MBIST, IEEE 1500, Diagnosis, Synopsys DFT tools, ATPG, LBIST, test compression, DFT architecture, Scan Insertion, Tessent
Skills:
boundary scan , Verilog, Python, MBIST, Synopsys, ATPG, Cadence Tools
Skills:
Perl, Python, Tcl, DFT rule compliance, low-power DFT methodologies, Modus EDT, ATPG test patterns, clock gating, IEEE 1149.1 JTAG, DFT architecture, power domain testing, IEEE 1500 standards, scan compression techniques, IJTAG, scan insertion strategies
Skills:
Verilog, Scan Insertion, Synopsys, DFT tools, systemverilog, Mentor Siemens Tessent, ATPG, Gate-Level Simulation, Cadence