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Job ID: 148565169
Skills:
boundary scan , Static Timing analysis, Perl, SDF, Tcl, ATPG vectors, TDL for ATE, formal verification tools, DFT simulation, tap controller, P1500, characterization DC Characteristics, MBIST insertion, Scan coverage, DFT tools from Mentor, netlist-based insertion flows
Skills:
ATPG, Scan Insertion, DFT methodologies, BIST techniques
Skills:
Vcs, System Verilog, primetime, Logic Equivalency checking, TetraMax, JTAG protocols, Tessent, Gate level simulation, ATPG, EDA Tools, BIST architectures, TestMax
Skills:
Perl, Python, Tcl, DFT rule compliance, low-power DFT methodologies, Modus EDT, ATPG test patterns, clock gating, IEEE 1149.1 JTAG, DFT architecture, power domain testing, IEEE 1500 standards, scan compression techniques, IJTAG, scan insertion strategies
Skills:
Tcl Scripting, Perl, Dft, Gate level simulations, Zero delay Timing Delay simulations, PD flow knowledge, ATPG Pattern generation, Timing Formal verification, JTAG P1500 protocols, SCAN DRC
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