boundary scan , Static Timing analysis, Perl, SDF, Tcl, ATPG vectors, TDL for ATE, formal verification tools, DFT simulation, tap controller, P1500, characterization DC Characteristics, MBIST insertion, Scan coverage, DFT tools from Mentor, netlist-based insertion flows

ATPG, Scan Insertion, DFT methodologies, BIST techniques

Vcs, System Verilog, primetime, Logic Equivalency checking, TetraMax, JTAG protocols, Tessent, Gate level simulation, ATPG, EDA Tools, BIST architectures, TestMax

Perl, Python, Tcl, DFT rule compliance, low-power DFT methodologies, Modus EDT, ATPG test patterns, clock gating, IEEE 1149.1 JTAG, DFT architecture, power domain testing, IEEE 1500 standards, scan compression techniques, IJTAG, scan insertion strategies

Tcl Scripting, Perl, Dft, Gate level simulations, Zero delay Timing Delay simulations, PD flow knowledge, ATPG Pattern generation, Timing Formal verification, JTAG P1500 protocols, SCAN DRC

Jtag, Python, Perl, Uvm, SV, Memory BIST, ATPG, NVIDIA custom tools

Python, scan pattern simulation, MBIST, DFT ATPG, automation flow development, AI ML-based engineering techniques, Tessent Modus, Debug

Python, Dft, Tessent, ATPG, Cadence Modus, MBIST