DFT Engineer
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Skills and Experience Required
Hands on experience in Inserting Scan and generating ATPG vectors for
Stuck-At and At-Speed Faults. In-depth experience in analysing and improving scan coverage
Hands on experience in MBIST (insertion and simulation)
Experience in Boundary Scan, inserting tap controller and P1500
Experience in RTL based and netlist-based insertion flows
Experience in DFT simulation with and without SDF Experience in Synthesis and formal verification tools
Experience in characterization (DC Characteristics)
Experience in generating TDL for ATE and working closely with ATE team during bring-up phase
Good exposure to DFT tools from Mentor, Synopsys and Cadence
Good scripting know-how in Perl and TCL
Experience in Static Timing analysis preferred
Educational Qualification: BE/ME or BTech /MTech
Job ID: 151697819
Skills:
Perl scripting, Delay Faults, Pattern Simulation, Siemens Tessent, Transition Faults, Synopsys TestMAX, Pattern Generation, DFT Compiler, Scan Insertion, DFT implementation, DFT DRC violations, ATPG, Cadence Modus, Stuck-at Faults
Skills:
Jtag, Perl, Verilog, Python, Tcl, gate-level DFT simulations, Scan Insertion, Cadence DFT EDA tools, MBIST, Siemens Tessent, Synopsys TestMAX, systemverilog, DFT implementation and verification, DFT rule checking, ATPG, scan chain stitching, Boundary Scan BSCAN
Skills:
boundary scan , Verilog, Python, Cadence Tools, ATPG, MBIST, Synopsys
Skills:
C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools
Skills:
Full Scan Compression, JTAG Boundary Scan, ATPG pattern generation, Scan chains, Fault Simulation
