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Showing 7 jobs
Skills:
Perl, Shell scripting, DFT verification, Synopsys Tetramax DFTMAX, VCS simulation tool, IEEE1500, Scan memory BIST, JTAG 1149.x, Verilog RTL design, Mentor testkompress, Design for Test methodologies
Skills:
Vcs, System Verilog, primetime, Logic Equivalency checking, TetraMax, JTAG protocols, Tessent, Gate level simulation, ATPG, EDA Tools, BIST architectures, TestMax
Skills:
Perl, Python, Tcl, coverage analysis, DFT tools, Tessent, ATPG, Scan Insertion, Cadence, DRC checks, Synopsys
Skills:
Jtag, Python, Perl, Uvm, SV, Memory BIST, ATPG, NVIDIA custom tools
Skills:
Tcl Scripting, Perl, Dft, Gate level simulations, Zero delay Timing Delay simulations, PD flow knowledge, ATPG Pattern generation, Timing Formal verification, JTAG P1500 protocols, SCAN DRC
Skills:
Constraints, Failure Analysis, physical design flow, Scan Insertion, silicon bring-up, DFT methodologies, Timing Analysis
Skills:
Perl, Python, Tcl, Applied Machine Learning, generative AI solutions, statistical tools for data analysis, DFT VLSI concepts
