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Job ID: 147869973
Skills:
industry-standard DFT EDA tools, DFT flow, Scan Insertion, timing generating test cases, verification for complex ASIC SoC designs, DFT validation, VLSI ASIC design flows, debugging GLS
Skills:
boundary scan , Static Timing analysis, Perl, SDF, Tcl, ATPG vectors, TDL for ATE, formal verification tools, DFT simulation, tap controller, P1500, characterization DC Characteristics, MBIST insertion, Scan coverage, DFT tools from Mentor, netlist-based insertion flows
Skills:
boundary scan , Digital Logic Design, Jtag, Perl, Verilog, Loopback, Python, Tcl, Timing Analysis, MBIST, DFT methodologies, Siemens Tessent, circuit fundamentals, compressed scan, IEEE 1500, IEEE 1687, ATPG coverage analysis, Cadence Modus, Genus, SDF-based simulations
Skills:
Compressor-based scan chain insertion, Analog BIST implementation
Skills:
Vcs, System Verilog, primetime, Logic Equivalency checking, TetraMax, JTAG protocols, Tessent, Gate level simulation, ATPG, EDA Tools, BIST architectures, TestMax
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