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DFT Engineer
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DFT Engineer
InfosysThis job is no longer accepting applications
Job Description
- Implement and validate Design for Test (DFT) features in complex SoCs
- Insert and verify: o Scan chains (Full Scan / Compression) o MBIST (Memory Built-In Self Test) o LBIST (Logic BIST) o JTAG / Boundary Scan
- Perform ATPG pattern generation & fault simulation
- Debug DFT-related issues in simulation and silicon
- Work closely with RTL, Physical Design, and Verification teams
- Support bring-up and production testing
- As part of the Infosys delivery team, your primary role would be to interface with the client for quality assurance, issue resolution and ensuring high customer satisfaction.
- You will understand requirements, create and review designs, validate the architecture and ensure high levels of service offerings to clients in the technology domain.
- You will participate in project estimation, provide inputs for solution delivery, conduct technical risk planning, perform code reviews and unit test plan reviews.
- You will lead and guide your teams towards developing optimized high quality code deliverables, continual knowledge management and adherence to the organizational guidelines and processes.
- You would be a key contributor to building efficient programs/ systems and if you think you fit right in to help our clients navigate their next in their digital transformation journey, this is the place for you! If you think you fit right in to help our clients navigate their next in their digital transformation journey, this is the place for you!
More Info
Key Skills
About Company
Skills:
Soc Architecture, Tcl, Python, Perl, HDLs, MBIST, ATPG flow implementation, UPF, Cadence digital implementation tools, DFT architecture definition, Tempus, CPF, Scan, Genus, tessent DFT, JTAG boundary scan
Skills:
Tcl Scripting, Perl, Dft, Gate level simulations, Zero delay Timing Delay simulations, PD flow knowledge, ATPG Pattern generation, Timing Formal verification, JTAG P1500 protocols, SCAN DRC Coverage debug, Scan Insertion
Skills:
Jtag, Perl, Verilog, Python, Tcl, Scan Insertion, Cadence DFT EDA tools, MBIST, Siemens Tessent, Synopsys TestMAX, systemverilog, DFT implementation and verification, DFT rule checking, ATPG, scan chain stitching, Boundary Scan BSCAN
Skills:
memory test , Digital Logic Design, static timing analysis, Hdl, Gate level scan insertion, test clocking, Scan ATPG compression techniques, ASIC Logic Design Flow, Scan ATPG, JTAG IEEE1149.1, DFT methodologies, Rtl Design, DFT architecture verification, security mechanisms, BIST architecture, ATPG configurations, post-silicon validation, Eco, JTAG boundary scan
Skills:
Built-In Self-Test (BIST), Test Methodologies, Scan chains