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DFT Engineer
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DFT Engineer
Infosys LimitedThis job is no longer accepting applications
Job Description
Responsibilities :
A day in the life of an Infoscion As part of the Infosys delivery team, your primary role would be to interface with the client for quality assurance, issue resolution and ensuring high customer satisfaction. You will understand requirements, create and review designs, validate the architecture and ensure high levels of service offerings to clients in the technology domain. You will participate in project estimation, provide inputs for solution delivery, conduct technical risk planning, perform code reviews and unit test plan reviews. You will lead and guide your teams towards developing optimized high quality code deliverables, continual knowledge management and adherence to the organizational guidelines and processes. You would be a key contributor to building efficient programs/ systems and if you think you fit right in to help our clients navigate their next in their digital transformation journey, this is the place for you! If you think you fit right in to help our clients navigate their next in their digital transformation journey, this is the place for you!Technical and Professional Requirements:
Implement and validate Design for Test (DFT) features in complex SoCs Insert and verify: o Scan chains (Full Scan / Compression) o MBIST (Memory Built-In Self Test) o LBIST (Logic BIST) o JTAG / Boundary Scan Perform ATPG pattern generation & fault simulation Debug DFT-related issues in simulation and silicon Work closely with RTL, Physical Design, and Verification teams Support bring-up and production testingMore Info
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Key Skills
About Company
Skills:
Jtag, Perl, Python, NVIDIA custom tools, Memory BIST, SV, ATPG, Uvm
Skills:
Jtag, MBIST, IEEE 1500, Diagnosis, Synopsys DFT tools, ATPG, LBIST, test compression, DFT architecture, Scan Insertion, Tessent
Skills:
logic bist , Unix, Jtag, Linux, Perl, Tcl, scan diagnostics, Verilog RTL, silicon debug, back-annotated gate level verification, Scan compression and insertion, ATPG, at-speed test, Memory BIST and repair scheme implementation, Fault Simulation, IJTAG
Skills:
boundary scan , Digital Logic Design, Jtag, Perl, Verilog, Loopback, Python, Tcl, DFT methodologies, Timing Analysis, MBIST, Siemens Tessent, circuit fundamentals, IEEE 1500, IEEE 1687, ATPG coverage analysis, compressed scan, Cadence Modus, Genus, SDF-based simulations
Skills:
Perl, Python, Tcl, DFT rule compliance, low-power DFT methodologies, Modus EDT, ATPG test patterns, clock gating, IEEE 1149.1 JTAG, DFT architecture, power domain testing, IEEE 1500 standards, scan compression techniques, IJTAG, scan insertion strategies