Perl scripting, Jtag, System Verilog, Sta, Compression, Synopsys DC, analog IP DfT simulations, timing simulations, Scan Insertion, RTL Coding, Lint checks, IJTAG, DfT Strategy, Memory BIST, Mentor DfT tools, ATPG coverage, silicon debug, SSN, simulator tools, primetime, Ate, ATPG, pattern delivery, Requirement Specification, DRC improvements

Perl scripting, Delay Faults, Pattern Simulation, Siemens Tessent, Transition Faults, Synopsys TestMAX, Pattern Generation, DFT Compiler, Scan Insertion, DFT implementation, DFT DRC violations, ATPG, Cadence Modus, Stuck-at Faults

Jtag, Perl, Verilog, Python, Tcl, gate-level DFT simulations, Scan Insertion, Cadence DFT EDA tools, MBIST, Siemens Tessent, Synopsys TestMAX, systemverilog, DFT implementation and verification, DFT rule checking, ATPG, scan chain stitching, Boundary Scan BSCAN

boundary scan , Static Timing analysis, Perl, SDF, Tcl, ATPG vectors, TDL for ATE, DFT simulation, formal verification tools, tap controller, P1500, characterization DC Characteristics, MBIST insertion, Scan coverage, DFT tools from Mentor, netlist-based insertion flows

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, UVM based verification frameworks, TLM

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools

Tcl Scripting, Perl, Dft, Gate level simulations, Zero delay Timing Delay simulations, PD flow knowledge, ATPG Pattern generation, Timing Formal verification, JTAG P1500 protocols, SCAN DRC Coverage debug, Scan Insertion

boundary scan , Digital Logic Design, Jtag, Perl, Verilog, Loopback, Python, Tcl, Timing Analysis, MBIST, DFT methodologies, Siemens Tessent, circuit fundamentals, compressed scan, IEEE 1500, IEEE 1687, ATPG coverage analysis, Cadence Modus, Genus, SDF-based simulations

boundary scan , Test Engineering, static timing analysis, Soc Architecture, Functional Testing, Test Execution, Testing, coverage analysis, lab equipment, debugging failures, Scan Insertion, EDA flows, MBIST, Cadence, Digital Design, Tessent, RTL synthesis, silicon bring-up, test architectures, test patterns, pattern generation, LBIST, Synopsys, ATPG tools

Perl, Shell scripting, DFT verification, Synopsys Tetramax DFTMAX, VCS simulation tool, IEEE1500, Scan memory BIST, Verilog RTL design, JTAG 1149.x, Design for Test methodologies, Mentor testkompress