logic bist , Jtag, PERL, Shell script, Python, E-fuse, Pattern Retargeting, BSDL, Pattern simulation, Post Silicon debug analysis, DFT architectures, IDDQ, Chip level DFT, Fault Models, ATPG Pattern generation, scan chain insertion and verification, SDC constructs for DFT modes, Digital design concepts, pattern generation for Memories, MBIST, Scan Compression Techniques, JTAG IJTAG, ATPG coverage analysis, Transition faults, stuck at, scan patterns and coverage statistics

industry-standard DFT EDA tools, DFT flow, Scan Insertion, timing generating test cases, verification for complex ASIC SoC designs, DFT validation, VLSI ASIC design flows, debugging GLS

boundary scan , Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, Tessent tool sets, TestMax

Vcs, ATE patterns, Scan Insertion, Tessent, JTAG protocols, ATPG, Gate level simulation, Post-silicon validation, P1687, TestMax, TetraMax

Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, Tessent tool sets, TestMax

Static Timing analysis, Stuck-At and At-Speed Faults, MBIST insertion and simulation, Boundary Scan inserting tap controller, Synthesis and formal verification tools, P1500, DFT tools from Mentor, characterization DC Characteristics, DFT simulation with and without SDF, generating TDL for ATE, RTL based and netlist-based insertion flows, Inserting Scan and generating ATPG vectors, analysing and improving scan coverage