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We are hiring for DFT Engineers.
Experience- 6+ years
Location- Across locations
Educational Qualification(s)
BE/ME
*Detailed Description of the Job Profile
• Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP tests and Pattern Validation w/wo Timing, DFT mode timing analysis and sign off.
• Be responsible for a comprehensive DFT plan and drive the implementation
• Work with DFT and cross functional teams
*Technical Skill [Required]
- Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Full-chip level
Must have experience of leading a team of 4-5members.
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Job ID: 145463025
Skills:
physical design flows, Scan Insertion, compression techniques, MBIST, Cadence, Mentor, STA synthesis, DFT tools, DFT architecture implementation, ATPG, LBIST, Synopsys
Skills:
Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, BScan, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, Tessent tool sets, TestMax
Skills:
Boundary Scan IJTAG, Scan ATPG, MBIST
Skills:
Shell, Jtag, Python, Tcl, Memory BIST, ATPG, Simulation, testbench development, Uvm, ATE pattern handling, systemverilog
Skills:
Vcs, System Verilog, JTAG protocols, Logic Equivalency checking, ATPG, Scan and BIST architectures, Gate level simulation debugging
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