DFT Engineer
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This job is no longer accepting applications
We are hiring for DFT Engineers.
Experience- 6+ years
Location- Across locations
Educational Qualification(s)
BE/ME
*Detailed Description of the Job Profile
• Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP tests and Pattern Validation w/wo Timing, DFT mode timing analysis and sign off.
• Be responsible for a comprehensive DFT plan and drive the implementation
• Work with DFT and cross functional teams
*Technical Skill [Required]
- Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Full-chip level
Must have experience of leading a team of 4-5members.
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Job ID: 145463025
Skills:
Jasper, Perl, Verilog, Debugging, Python, Tcl, Xcelium, Memory Test methodologies, Modus, Scan Insertion, VHDL, ATPG, Genus, silicon bring-up
Skills:
Vcs, ATE patterns, Scan Insertion, JTAG protocols, Tessent, Gate level simulation, ATPG, Post-silicon validation, P1687, TestMax, TetraMax
Skills:
Spi, Verilog, I2c, System Verilog, Scan Insertion, Digital DFT design, Logicbist, Mentor, Cadence, TetraMax, Gate level simulations, Synthesis, AMBA, ATPG, Digital RTL coding, Timing Constraints, Synopsys, PMIC
Skills:
Soc Architecture, Tcl, Python, Perl, HDLs, MBIST, ATPG flow implementation, UPF, Cadence digital implementation tools, DFT architecture definition, Tempus, CPF, Scan, Genus, tessent DFT, JTAG boundary scan
Skills:
boundary scan , Vcs, System Verilog, Memory BIST, JTAG protocols, ATPG, Logic Equivalency checking, Scan and BIST architectures, Gate level simulation debugging
