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We are hiring for DFT Engineers.
Experience- 6+ years
Location- Across locations
Educational Qualification(s)
BE/ME
*Detailed Description of the Job Profile
• Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP tests and Pattern Validation w/wo Timing, DFT mode timing analysis and sign off.
• Be responsible for a comprehensive DFT plan and drive the implementation
• Work with DFT and cross functional teams
*Technical Skill [Required]
- Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Full-chip level
Must have experience of leading a team of 4-5members.
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Job ID: 145463025
Skills:
boundary scan , Jtag, Perl, Python, Tcl, MBIST, Siemens Tessent, Insertion Coverage Analysis, Static Verification, Synopsys TestMAX, TetraMax, Cadence Modus, ATPG, Scan Compression, DRC Rule Checks, LBIST, EDA Tool Proficiency, DFT Architecture
Skills:
Vcs, ATE patterns, Scan Insertion, JTAG protocols, ATPG, Post-silicon validation, Tessent tool sets, P1687, TestMax, TetraMax, Gate level simulation debugging
Skills:
Vcs, Static Timing Analysis, ATPG tools, Verdi, DFT ATPG, FSDB, Debug skills, Scripting skills, Timing Closure, Synopsys Tetramax, Scan Patterns, Mentor Graphics, Siemens, ATPG scripts
Skills:
rtl verification , SoC-level DFT architecture implementation, LINT, Synthesis, ATPG, DFT timing, DFT Embedded Deterministic Test EDA tool Tessent, SoC DFT RTL implementation, MBIST, Low Power designs
Skills:
boundary scan , bist , DFT Engineering, Pattern Retargeting, Coverage analysis and improvement, Scan Chains, Xelium, Synopsys DFT Compiler, Scan Insertion, ATPG, DFT DRC Debugging and Resolution, Test Kompress
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