physical design flows, Scan Insertion, compression techniques, MBIST, Cadence, Mentor, STA synthesis, DFT tools, DFT architecture implementation, ATPG, LBIST, Synopsys

Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, BScan, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, Tessent tool sets, TestMax

Boundary Scan IJTAG, Scan ATPG, MBIST

Shell, Jtag, Python, Tcl, Memory BIST, ATPG, Simulation, testbench development, Uvm, ATE pattern handling, systemverilog

Vcs, System Verilog, JTAG protocols, Logic Equivalency checking, ATPG, Scan and BIST architectures, Gate level simulation debugging

Vcs, Static Timing Analysis, Verdi, ATPG tools, DFT ATPG, TetraMax, FSDB, Debug skills, Scripting skills, Timing Closure, Scan Patterns, Siemens, Mentor Graphics, Synopsys, ATPG scripts

Vcs, Static Timing Analysis, Scan Insertion, Post-silicon validation, P1687, TetraMax, ATE patterns, JTAG protocols, ATPG, Gate level simulation, Tessent tool sets, TestMax

Vcs, Static Timing Analysis, Scan Insertion, Post-silicon validation, P1687, TetraMax, ATE patterns, JTAG protocols, Gate level simulation, ATPG, Tessent tool sets, TestMax