Search by job, company or skills

  • Posted a month ago
  • Be among the first 20 applicants
Early Applicant
Quick Apply

Job Description

  • Min 4+ Years of Relevant Experience in DFT and candidate will be responsible for Designing and Implementing DFT techniques.
  • Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability.
  • Test Modes implementation and verification, scan insertion including on-chip compression.
  • Implementing, integrating and verifying memory BIST and boundary scan.
  • ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test Coverage and simulations at gate level with timing (SDF).
  • Basic understanding of complete SOC design and flow.
  • Cross functional teams interaction for issue resolution.
  • Participate in driving new DFT methodology and solutions to improve quality, reliability and insystem test and debug capability.
  • Hiring candidate with these specific personal characteristic and qualifications.
  • Mentoring junior engineers and drive innovation/automation.
  • Excellent in problem solving and analytical skills.
  • Excellent communication, team work and networking skills.

More Info

Job Type:
Function:
Employment Type:
Open to candidates from:
Indian

About Company

Capgemini is an AI-powered global business and technology transformation partner, delivering tangible business value. We imagine the future of organizations and make it real with AI, technology and people. With our strong heritage of nearly 60 years, we are a responsible and diverse group of 420,000 team members in more than 50 countries. We deliver end-to-end services and solutions with our deep industry expertise and strong partner ecosystem, leveraging our capabilities across strategy, technology, design, engineering and business operations. The Group reported 2024 global revenues of €22.1 billion.

Job ID: 131355329

Similar Jobs