THE PERSON:
You will lead by bringing people together and drive towards consensus, decisions, and results. Working independently, you will convert high level concepts down to tangible specifications that can be implemented efficiently. You should enjoy collaborating with engineers with their diverse skillsets and bring their expertise to bear on solving challenging Programable Clock problems.
KEY RESPONSIBILITIES:
- Lead floor-planning, placement, routing, custom clock tree design, and optimization.
- Expert knowledge and hands-on experience of the entire backend and adjacent flows, including synthesis, Floor-planning P&R, clocking, timing closure, power and IO planning
- Perform all aspects of design flow from feasibility analysis, logic synthesis, FP, place and route, FEV, power, timing, quality checks, and design closure.
- Collaborate with design, Physical design, IT/infrastructure teams to ensure successful CAD flow all the way from IP design to SoC/3DIC design.
- Developing Programable global Clock distribution methodologies, optimizing Clock - Skew, Signal integrity and power integrity issues for AMDs next generation of programmable product families.
- Large Scale Block to Block Clock timing analysis, within the Die & Die to Die Clock interposer crossing.
- Deep analysis of timing paths to identify and debug key issues.
- Collaborate with functional IP teams (RTL, Ckt, physical design, Full Chip Timing, Integration) during the implementation and qualification of a growing number of programable Clock IPs.
PREFERRED EXPERIENCE:
- You should have a deep understanding of clocking methodologies and experience in leading teams to deliver complex projects. Working knowledge of Programable clocking is a plus.
- Strong working knowledge in all aspects of Physical Design and Advanced Packaging (Professional Experience: 10+ years of hands-on experience in physical design and verification, with a proven track record in chip-level PNR and successful tapeouts of complex SoC designs).
- You should be an expert in the development of clocking solutions and have the ability to work effectively with global teams (USA & India) to ensure that on time product delivery with high quality is met.
- Strong Clock fundamentals (Clock switching and gating, synchronization, Clock skew balancing, Jitter, Fmax, DCD and CDC analysis).
- Familiarity with test, debug, yield, post-Silicon Validation & Characterization is a plus.
- Working experience of Package level Clock SIPI is a plus.
- Proficient in STA and methodologies for timing closure and have a good understanding of noise, cross-talk, Aging and OCV effects, among others.Defined timing/SDC and placement constraints for IPs.
- Familiar with circuit modeling, including SPICE models, and worst-case corner selection.
- Familiarity with Verilog and system Verilog for design.
- Additionally, you should be a skilled communicator, able to provide technical guidance and mentorship to junior team members to help them develop their skills and advance their careers.
ACADEMIC CREDENTIALS:
- Bachelor or master degree in computer engineering/Electronics or Electrical Engineering with 8-12+ years of exp.
