About The Role
Senior technical leadership position having minimum 10+ years of experience responsible for ASIC/RTL design verification, team management, and implementation of verification strategies using advanced tools and methodologies.
Key Responsibilities
- Lead and manage verification team of 10+ members (Must have)
- Develop and implement verification strategies using System Verilog
- Oversee OVM/UVM implementation and verification processes
- Manage simulation environments across multiple platforms (Synopsys/Mentor Graphics/Cadence)
- Drive scripting and automation initiatives
- Lead debugging and analysis of complex digital design issues
- Oversee verification of processor subsystems
- Manage validation suite creation and automation
- Guide silicon bring up and testing processes
- Ensure quality and completeness of verification deliverables
Qualifications & Skills
- B.E/B.Tech/M.E/M.Tech in Electrical/Electronic Engineering
- 10+ years in ASIC/RTL design verification
- System Verilog Testbench Architecture, OVM, UVM expertise, Simulator tools (Synopsys/Mentor Graphics/Cadence)
- Scripting languages (Perl, Python, Shell, Tcl/Tk), Hardware verification languages (SystemVerilog, SystemC), Hardware description languages (Verilog, VHDL), AMBA, AHB, AXI
- JTAG protocols, Gate-Level Simulation and Debugging, Processor subsystems (ARM/RISC), Silicon testing and bench application.
