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Design Verification Lead
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L&T Technology services is looking to hire for Design Verification Engineers for Lead Role.
Job Location : Bangalore
Experience : 7-10 Years
Job details are as below ::
Job Description DV Positions:
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification
Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Debug, root-cause and resolve functional failures in the design, partnering with the Design team
Qualifications and Skills for DV Positions:
Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience
8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification
8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies
Experience in development of UVM based verification environments from scratch
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs
Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet
Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
Experience with revision control stems like Mercurial(Hg), Git or SVN
Job ID: 153641001
Skills:
Usb, Vcs, DDR, Pcie, Perl, Python, Tcl, Uvm, systemverilog, Axi, DVE, Modelsim, AHB
Skills:
Unix, Usb, Linux, System Verilog, Jtag, Ethernet, Python, Perl, Pcie, TSN, UVM methodology, Design for Debug, ARM based SoC verification
Skills:
Usb, Mac, Perl, Pcie, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB
Skills:
Tcl Scripting, Doors, Knowledge of Hardware Board and different components like ADC DAC Serial Memory, DO-254 development process, Electronics Electrical Engineering, Hardware system design knowledge of digital logic, RTL development using VHDL, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, FPGA Synthesis Place and Route, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, Requirement analysis and validation, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA design tools like Libero
Skills:
DDR, Usb, Pcie, Ethernet, SV, CXL, Uvm
