Usb, Vcs, DDR, Pcie, Perl, Python, Tcl, Uvm, systemverilog, Axi, DVE, Modelsim, AHB

Unix, Usb, Linux, System Verilog, Jtag, Ethernet, Python, Perl, Pcie, TSN, UVM methodology, Design for Debug, ARM based SoC verification

Usb, Mac, Perl, Pcie, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Tcl Scripting, Doors, Knowledge of Hardware Board and different components like ADC DAC Serial Memory, DO-254 development process, Electronics Electrical Engineering, Hardware system design knowledge of digital logic, RTL development using VHDL, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, FPGA Synthesis Place and Route, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, Requirement analysis and validation, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA design tools like Libero

DDR, Usb, Pcie, Ethernet, SV, CXL, Uvm

Doors, Tcl Scripting, FPGA Synthesis Place and Route, DO-254 development process, RTL development using VHDL, Hardware system design knowledge of digital logic, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, FPGA design tools like Libero, Electronics Electrical Engineering, Knowledge of Hardware Board and different components like ADC DAC Serial Memory

Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, SystemVerilog UVM, Axi, CXL, SVA

Soc Architecture, System Verilog, digital design concepts, UVM Universal Verification Methodology, debugging using waveforms and logs