Design Verification Engineer

Company Description www.prajnov.com

Role Description

Title: Design Verification Engineer

Experience: 6+ years

Location: Bangalore / Kochi

We are looking for a hands-on Design Verification Engineer with strong SystemVerilog/UVM experience and exposure to live semiconductor/SoC projects.

Key Responsibilities

• Develop and maintain SystemVerilog/UVM verification environments

• Build monitors, checkers, scoreboards and assertions

• Develop random/constrained-random stimulus and functional coverage

• Work with AMBA protocols and ARM CPU

• Debug complex design and verification issues

• Collaborate with RTL/design and cross-functional teams

• Automate verification activities using Python / Perl / Shell / Makefile

Required Skills

Strong SystemVerilog & UVM

Hands-on functional verification experience

Good knowledge of AMBA protocols & ARM CPU

Unix/Linux environment and verification tools

Configuration management, bug tracking and verification dashboards

Good to Have

• PCIe and/or Ethernet protocol experience

• Python / Perl / Shell scripting

• Experience with verification automation and regression

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