P
Design Verification Engineer
P
Design Verification Engineer
pqangels technologies pvt. ltd.- Posted 13 hours ago
- Be among the first 10 applicants
Job Description
ASIC / SoCDesign Verification Engineer
Company: PQAngels Technologies Pvt. Ltd.
Location: Bengaluru
Experience: 5 -11 Years
Employment Type: Full-Time
About the Role
PQAngels Technologies is looking for experienced Design Verification Engineers to work on challenging ASIC, SoC, and Subsystem verification projects.
We are looking for engineers with strong hands-on expertise in SystemVerilog and UVM, along with experience verifying complex designs and high-speed interfaces.
What You Will Work On
- Develop and enhance SystemVerilog/UVM-based verification environments
- Create verification plans, test strategies, test scenarios and test cases
- Perform functional verification at IP, Subsystem and SoC levels
- Develop reusable UVM components and verification infrastructure
- Implement SystemVerilog Assertions (SVA)
- Analyze functional coverage and drive coverage closure
- Execute simulations, regressions and debug failures
- Perform RTL/testbench debugging and root-cause analysis
- Verify high-speed protocols and interfaces
- Support verification signoff and project closure
- Work closely with RTL, Architecture, Integration and other engineering teams
- Participate in technical reviews and customer discussions when required
Must-Have Skills
- 5-11 years of relevant Design Verification experience
- Strong hands-on SystemVerilog
- Strong hands-on UVM
- Experience with Functional Coverage
- Good experience in SVA
- ASIC / SoC / Subsystem / IP verification experience
- Strong debugging and root-cause analysis skills
- Experience with one or more high-speed interfaces:
- PCIe
- DDR / DDR4 / DDR5 / LPDDR
- USB
- Ethernet
- NoC
- Scripting knowledge in Python / Perl / TCL
- Good understanding of ASIC/VLSI verification methodology and flow
Verification Tools
- Education: B.E./B.Tech/M.E./M.Tech in ECE, Electrical, Electronics, VLSI, Microelectronics or related fields.
More Info
Job Type:
Industry:
Function:
Employment Type:
About Company
Skills:
C, Pcie, Perl, Python, Tcl, UFS, HSIO PHY Controllers, Skill, Open Verification Methodology, USB2, systemverilog, MIPI, USB3, Universal Verification Methodology
Skills:
Bug Tracking, Configuration management, Makefile, Perl, Shell scripting, Python, Verification automation, ARM CPU, AMBA protocols, Regression, SystemVerilog UVM, Verification dashboards, Unix Linux environment, Verification Tools
Skills:
Shell, Perl, Python, Tcl, Cadence Xcelium, Mentor QuestaSim, PCI Express, Uvm, systemverilog, Synopsys VCS, Assertion-Based Verification, Constrained Random Verification, Functional Verification
Skills:
code coverage , RTL and digital design concepts, systemverilog, Constrained-random verification, UVM methodology, Simulation and debugging tools, Functional coverage, Assertions
Skills:
DDR, Ethernet, System Verilog, RISC-V cores, SV coverpoints, GIC, CMN, AXI protocol, SMMU, Low-power verification, PCle, Cache and coherency verification, Uvm, UPF, ACE protocol, eMMC, CoreSight, Low-speed peripherals, ARM v8 and v7 cores, Assembly