C, Pcie, Perl, Python, Tcl, UFS, HSIO PHY Controllers, Skill, Open Verification Methodology, USB2, systemverilog, MIPI, USB3, Universal Verification Methodology

Noc, Usb, DDR, Pcie, Perl, Ethernet, Python, Tcl, Functional Coverage, Uvm, systemverilog, LPDDR, DDR5, DDR4, SVA

Shell, Perl, Python, Tcl, Cadence Xcelium, Mentor QuestaSim, PCI Express, Uvm, systemverilog, Synopsys VCS, Assertion-Based Verification, Constrained Random Verification, Functional Verification

code coverage , RTL and digital design concepts, systemverilog, Constrained-random verification, UVM methodology, Simulation and debugging tools, Functional coverage, Assertions

Usb, DDR, Perl, Pcie, Ethernet, Python, Tcl, Uvm, coverage-driven verification, systemverilog, digital design RTL understanding, AMBA, MIPI, SVA

C, Perl, Python, Tcl, IP-XACT, Uvm, UPF, systemverilog, GLS, Axi, SystemRDL, APB, Tk, AHB, RAL

Pcie, Regression Testing, Verilog, Ethernet, assertions, Uvm, systemverilog, functional coverage, constrained-random verification

C, C++, Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, Post-silicon debugging, RTL design and verification flows, Simulation Tools, JTAG protocols, Digital Design, Assembly language programming

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog