C, Pcie, Perl, Python, Tcl, UFS, HSIO PHY Controllers, Skill, Open Verification Methodology, USB2, systemverilog, MIPI, USB3, Universal Verification Methodology

Bug Tracking, Configuration management, Makefile, Perl, Shell scripting, Python, Verification automation, ARM CPU, AMBA protocols, Regression, SystemVerilog UVM, Verification dashboards, Unix Linux environment, Verification Tools

Shell, Perl, Python, Tcl, Cadence Xcelium, Mentor QuestaSim, PCI Express, Uvm, systemverilog, Synopsys VCS, Assertion-Based Verification, Constrained Random Verification, Functional Verification

code coverage , RTL and digital design concepts, systemverilog, Constrained-random verification, UVM methodology, Simulation and debugging tools, Functional coverage, Assertions

DDR, Ethernet, System Verilog, RISC-V cores, SV coverpoints, GIC, CMN, AXI protocol, SMMU, Low-power verification, PCle, Cache and coherency verification, Uvm, UPF, ACE protocol, eMMC, CoreSight, Low-speed peripherals, ARM v8 and v7 cores, Assembly

Perl, Python, Tcl, Functional Coverage, Uvm, SVA, systemverilog, ASIC SoC Subsystem IP verification

C, Perl, Python, Tcl, IP-XACT, Uvm, UPF, systemverilog, GLS, Axi, SystemRDL, APB, Tk, AHB, RAL

Pcie, Regression Testing, Verilog, Ethernet, assertions, Uvm, systemverilog, functional coverage, constrained-random verification

C, C++, Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, Post-silicon debugging, RTL design and verification flows, Simulation Tools, JTAG protocols, Digital Design, Assembly language programming