Design Verification Engineer

Usb, Vcs, DDR, Pcie, Ethernet, System Verilog, Xcelium, UVM methodology, UCIE, Axi, Questa, CXL

C, coverage closure, microprocessor ISA, coverage planning, Data-Consistency verification, power management verification, testbench development, clocking reset power-up sequences, low power verification flows, systemverilog

Verilog, System Verilog, Assertion Checker Development, Coverage Closure, Functional Coverage Development, Testcase Planning Development, UVM Testbench Coding, Design Verification Failure Debugging, Concepts in Digital Design

System Verilog, SV UVM based test benches, scripting languages such as Perl, HDLs like Verilog, debugging RTL TB issues using Verdi or similar tools

Vcs, System Verilog, Verdi, DVE, Xcelium, Questa, Uvm, SVA assertions