Design Verification Engineer
Design Verification Engineer
ALTEN Calsoft Labs- Posted 14 hours ago
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Job Description
Design Verification Engineers
Location: Hyderabad
Hiring: SystemVerilog / UVM Verification Engineer (3+ Years)
ACL Digital is looking for a proactive Verification Engineer with 3+ years of experience to join our team in Hyderabad. You will be responsible for developing block/IP level testbenches, handling Vplan execution, regression management, real number modeling, and Gate Level Simulations (GLS). Experience with subsystem/SoC verification is a plus, and candidates must have a notice period of 0–30 days.
To apply, send your updated resume directly to [Confidential Information].
More Info
Key Skills
Gate Level Simulations
subsystem SoC verification
real number modeling
regression management
Vplan execution
About Company
Skills:
C, Debugging, Verilog RTL, Verification Techniques, Communication Interfaces, Scripting and Automation, EDA Tools, Uvm, Digital and SoC Verification, C DPI, systemverilog
Skills:
Scripting Language, Python, SV, IJTAG protocol, Functional coverage analysis, Test bench development, Test cases coding, Uvm
Skills:
Unix, Shell, Pcie, Linux, System Verilog, Python, VIP coding, Constraint based Random verification, Coverage strategies and measurement, Skill, Test cases coding, Cadence, Mentor, Uvm, Digital Design and Verification methodologies, DDR verification, Synopsys simulation suites, EDA Tools, Verilator, Test Plan design
Skills:
Verilog, System Verilog, Cadence IES, Synopsys VCS, Uvm, formal property checking tools
Skills:
Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm