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We need experienced engineers to verify an IP/full-chip using System Verilog/UVM. Expertise in PCIe/DDR verification is preferable at IP/chip level.
Skills:
Traits:
Job ID: 148676469
Skills:
arm architecture , AI ML SoC exposure, Gate-Level Simulation, Cadence Tools, Arm Corestone, ATE pattern generation support, Test Bench Development, SystemVerilog UVM, ASIC SOC verification, Low-power verification experience, Functional Verification, AXI AHB APB Protocols
Skills:
Usb, C, Makefile, Windows, Shell, Pcie, Linux, Perl, Verilog, Ethernet, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools, UVM testbenches, automating workflows in a distributed compute environment, AXI ACE Protocols, simulation profile efficiency improvement, UVM based verification frameworks, TLM, debugging firmware and RTL code using simulation tools
Skills:
C, Systemc, Windows, Usb, Linux, Makefile, Shell, Verilog, Ruby, System Verilog, Ethernet, Pcie, Perl, automating workflows in a distributed compute environment, graphics pipeline knowledge, debugging firmware and RTL code using simulation tools, IP level ASIC verification, AXI ACE Protocols, UVM testbenches, HLS tools, TLM, UVM based verification frameworks, simulation profile efficiency improvement
Skills:
Test Plans, Nvme, DDR, Pcie, coverage analysis, UVM methodology, systemverilog, Axi, RTL debugging, testbenches, assertions, AHB
Skills:
Verilog, Tcl, Python, Perl, VHDL, Uvm, systemverilog
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