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Design Verification Engineer
Sevya Multimedia

Design Verification Engineer

Sevya Multimedia
3-5 Years
Not Disclosed
Early Applicant
  • Posted 2 months ago
  • Be among the first 20 applicants

Job Description

We need experienced engineers to verify an IP/full-chip using System Verilog/UVM. Expertise in PCIe/DDR verification is preferable at IP/chip level.

Skills:

  • Overall 3+ years industry experience in Design Verification using System-Verilog/C/UVM.
  • Generic knowhow on Digital Design and Verification methodologies.
  • Experience in System Verilog/UVM based IP/SoC verification using advanced technologies.
  • Good understanding of Constraint based Random verification; VIP coding; Test Plan design; Test cases coding; Coverage strategies and measurement
  • Proficient in EDA tools used for Design Verification (e.g. Cadence/Mentor/Synopsys simulation suites; Verilator).
  • Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability.
  • Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills

Traits:

  • Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.
  • Solutions orientation; Quality driven; Execution minded

More Info

Job Type:
Permanent Job
Industry:
Other
Function:
Engineering
Employment Type:
Full time

Key Skills

VIP coding

Coverage strategies and measurement

Constraint based Random verification

Skill

Test cases coding

Uvm

Digital Design and Verification methodologies

Python Script

DDR verification

Test Plan design

Unix

Shell

Pcie
Linux
System Verilog

About Company

Last Updated: 16-10-2026 02:23:03 AM

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